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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. features ? 450 mhz small signal bandwidth ?1500v/ s slew rate ? 5.2 ma/channel static supply current ? 65 ma output current ? 120 mhz gain flatness to +/- 0. 1db ? 14 pin soic applications ? video switchers/routers ? video line drivers ? twisted pair driver/receiver ? active filters description the zl40122 is a high speed, quad, current feedback operational amplifier offering high performance at a low cost. the device has a very high output current drive capability of 65 ma while requiring only 5.2 ma of static supply current. this feature makes the zl40122 the ideal choice where a high density of high speed devices is required. the flat gain response to 120 mhz, 450 mhz small signal bandwidth and 1500 v/ s slew rate make the device an excellent solution for video applications such as driving video signals down significant cable lengths. other applications which may take advantage of the zl40122 superior dynamic performance features include low cost high order active filters and twisted pair driver/receivers. november 2004 ordering information zl40122/dca 14 lead soic tubes zl40122/dcb 14 lead soic tape & reel zl40122dcb1 14 lead soic* tape & reel ZL40122DCA1 14 lead soic* tubes *pb free matte tin -40 c to +85 c zl40122 high speed, current feedback quad operational amplifier data sheet figure 1 - functional block diagram and pin connection 7 out_1 in_n_1 in_p_1 in_p_2 in_n_2 out_2 out_4 in_n_4 in_p_4 v- in_p_3 in_n_3 out_3 zl40122 v+ 1 2 3 4 5 6 8 9 10 11 12 13 14 1 23 4
zl40122 data sheet 2 zarlink semiconductor inc. application notes current feedback op amps current feedback op amps offer several advantages over voltage feedback amplifiers: ? ac bandwidth not dependent on closed loop gain ? high slew rate ? fast settling time the architecture of the current feedback opamp consis ts of a high impedance non-inverting input and a low impedance inverting input which is always feedback connec ted. the error current is amplified by a transimpedance amplifier which can be considered to have gain where z o is the dc gain. it can be shown that the closed loop non-inverting gain is given by where av is the dc closed loop gain, r f is the feedback resistor. the closed l oop bandwidth is therefore given by and for low values of closed loop gain av depends only on the feedback resistor r f and not the closed loop gain. increasing the value of r f ? increases closed loop stability ? decreases loop gain ? decreases bandwidth ? reduces gain peaking ? reduces overshoot using a resistor value of r f =510 ? for av=+2 v/v gives good stability and bandwidth. however since requirements for stability and bandwidth vary it may be worth experimentation to find the optimal r f for a given application. layout considerations correct high frequency operation requires a considered pc b layout as stray capacitances have a strong influence over high frequency operation for this de0ice. the zarlin k evaluation board serves as a good example layout that should be copied. the following guidelines should be followed: ? include 6.8 uf tantalum and 0.1 uf ceramic capacitors on both positive and negative supplies ? remove the ground plane under and around the part, espe cially near the input and output pins to reduce parasitic capacitances ? minimize all trace lengths to reduce series inductance ? ? ? ? ? ? ? ? + = o o f f j z f z 1 ) ( ? ? ? ? ? ? ? ? + = o o f z f fr j av vin vout 1 f ol f o o cl r gb r z f bw = =
zl40122 data sheet 3 zarlink semiconductor inc. application diagrams figure 2 - non-inverting gain figure 3 - inverting gain 6.8uf 0.1uf 0.1uf 6.8uf vcc vin vout rin ra rf vee ? zl40122 ra rf av vin vout + = = 1 ? ? ? ? ? ? ? ? ? 6.8uf 0.1uf 0.1uf 6.8uf vcc vin vout rin ra rf vee ? zl40122 rb ra rf av vin vout ? = = ? ? ? ? ? ? ? ? ?
zl40122 data sheet 4 zarlink semiconductor inc. absolute maximum ratings note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. for guaranteed specifications and the test conditions, see the electrical characteristics. note 2: human body model, 1.5 k ? in series with 100 pf. machine model, 20 ? in series with 100 pf. note 3: 0.8 kv between the pairs of +ina, -ina and +inb pins on ly. 2 kv between supply pins, outa or outb pins and any input pin. note 4: 100 ma applied to input and output pins to force the device to go into "latch-up". the device passes this test to jedec spec 17. note 5: positive and negative supply transient testing increases the supplies by 20% for 100 ms. operating range parameter symbol min. max. units 1 vin differential v in 1.2 v 2 output short circuit protection v os/c see apps note in this data sheet 3 supply voltage v+, v- 6.5 v 4 voltage at input pins v (+in) , v (-in) v- v+ v 5 voltage at output pins v o v- v+ v 6 eds protection (hbm human body model) (see note 2) 2 (see note 3) kv 7 storage temperature -55 +150 c 8 latch-up test 100 ma for 100 ms (see note 4) 9 supply transient test 20% pulse for 100 ms (see note 5) characteristic min. typ. max. units comments supply voltage (vcc) 4.0 6.0 v operating temperature (ambient) -40 +85 c junction to ambient resistance rth(j-a) 150 c 4 layer fr4 board junction to case resistance rth(j-c) 60 c 4 layer fr4 board
zl40122 data sheet 5 zarlink semiconductor inc. electrical characteristics - vcc= 5 v, t amb =25c(typ.),t amb =-40c to +85c(min-max), av=+2v/v, rf=510 ? , rload=100 ? unless specified. characteristic conditions typ 25c min/ max 25c min/ max ? 40 to +85c units test type 1 frequency domain response -3 db bandwidth av=+1; vo < 0.5 vp-p; rf=1.5 k ? 450 - - mhz c av=+2; vo < 0.5 vp-p; rf=510 ? 380 - - mhz c av=+2; vo < 5 vp-p; rf=510 ? 170 - - mhz c +/- 0.1 db flatness av=+2; vo < 0.5 vp-p; rf=510 ? 120 - - mhz c differential gain (ntsc) rload=150 ? 0.01 - - % c differential phase (ntsc) rload=150 ? 0.015 - - deg. c time domain response rise and fall time vout=0.5 v step 1 - - ns c vout=5 v step 2.8 - - ns c settling time to 0.1% vout=2 v step 6 - - ns c overshoot vout=0.5 v step 4 - - % c slew rate vout=5 v step 1500 - - v/ sc noise and distortion 2 nd harmonic distortion vout=2 vp-p, 1 mhz -84 - - dbc c 3 nd harmonic distortion vout=2 vp-p, 1 mhz -85 - - dbc c equivalent input noise voltage >1 mhz 5.5 - - nv c non-inverting current >1 mhz 1.3 - - pv c inverting current >1 mhz 11 - - pa c static, dc performance input offset voltage 2.7 6.3 7.7 mv a average drift - - 15 v/deg. c c input bias current ? non-inverting 2.6 5.6 6uaa average drift - - 6 na/deg. c c hz hz hz
zl40122 data sheet 6 zarlink semiconductor inc. note: test types: (a) 100% tested at 25 c. over temperature limits are set by characterization and simulation. (b) limits set by characterization or simulation. (c) typical value on ly for in formation. input bias current ? inverting 7.4 25 28 aa average drift - - 15 na/deg. c c power supply rejection ratio (+ve) dc 61 58 57 db a power supply rejection ratio (-ve) dc 58 56 55 db a common mode rejection ratio dc 54 50 49 db a supply current (per channel) quiescent 5.2 6.5 6.7 ma a miscellaneous performance input resistance (non-inverting) 8 - - m ? c input capacitance (non-inverting) 1 - - pf c common mode input range 2.4 2.2 2.0 v a output voltage range rload=100 ? 2.8 2.7 2.6 v a output current (max) 65 - - ma c output resistance, closed loop dc 90 - - m ? c characteristic conditions typ 25c min/ max 25c min/ max ? 40 to +85c units test type 1
zl40122 data sheet 7 zarlink semiconductor inc. typical performance characteristics - t amb =25degc, v supply = 5 v, rload=100 ? , av=+2v/v, rf=510 ? , unless otherwise specified . non-inverting frequency response -14 -12 -10 -8 -6 -4 -2 0 2 1 10 100 1000 frequency (mhz) normalised gain (db) -200 -150 -100 -50 0 50 100 150 200 phase (deg.) a v =+8 rf = 150 a v =+4 rf = 150 a v =+2 rf = 510 a v =+1 rf = 1k gain phase vo=0.5vp-p
zl40122 data sheet 8 zarlink semiconductor inc. non-inverting frequency response varying rf -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 10 100 1000 frequency (mhz) normalised gain (db) rf=390 rf=250 rf=700 rf=510 vo=0.5vp-p open loop transimpedance gain and phase 40 50 60 70 80 90 100 110 120 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 1.0e+09 frequency (hz) transimpedance gain -240 -210 -180 -150 -120 -90 -60 -30 0 transimpedance phase transimpedance phase transimpedance gain
zl40122 data sheet 9 zarlink semiconductor inc. large signal gain -16 -14 -12 -10 -8 -6 -4 -2 0 10 100 1000 frequency (mhz) gain (db) vo = 5v p-p vo = 4v p-p vo = 1v p-p harmonic distortion vs frequency -100 -90 -80 -70 -60 -50 -40 110100 frequency (mhz) 2nd & 3rd harmonic distortion (dbc) 2nd harmonic 3rd harmonic vo = 2v p-p
zl40122 data sheet 10 zarlink semiconductor inc. cmrr 0 10 20 30 40 50 60 70 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) rejection ration (db) t = - 40 degc t = + 25 degc t = + 85 degc psrr +ve 0 10 20 30 40 50 60 70 80 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) rejection ration (db) t = - 40 degc t = + 25 degc t = + 85 degc
zl40122 data sheet 11 zarlink semiconductor inc. psrr -ve 0 10 20 30 40 50 60 70 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) rejection ration (db) t t t t t t t = - 40 degc t = + 25 degc t = + 85 degc input voltage and current noise 1 10 100 1.0e+01 1.0e+02 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 frequency (hz) current noise (pa/sqrt(hz) voltage noise (nv/sqrt(hz) input voltage noise inverting input current noise non-inverting input current
zl40122 data sheet 12 zarlink semiconductor inc. supply current vs temperature 4.70 4.80 4.90 5.00 5.10 5.20 5.30 5.40 5.50 5.60 -40 -20 0 20 40 60 80 100 120 140 die temp (deg. c) supply current (ma) dc drift over temperature 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 -40 -20 0 20 40 60 80 100 120 140 die temp (deg. c) input offset voltage (mv) input bias current (ua) input bias inv input bias non-inv input offset voltage
zl40122 data sheet 13 zarlink semiconductor inc. large and small signal pulse response -3 -2 -1 0 1 2 3 0 1020304050607080 time (ns) large signal vout (v ) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 small signal vout (v ) vout = 5v step vout = 0.5v step closed loop output impedance 0.01 0.1 1 10 0.01 0.1 1 10 100 frequency (mhz) closed loop output impedance (ohms)
zl40122 data sheet 14 zarlink semiconductor inc. differential gain & phase zl40122 / zl40123 ntsc rl=150? -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 bias voltage differential gain & phase (?% & ? ) best fit gain best fit phase
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes
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